Camera. CXA1390AQ Datasheet

CXA1390AQ Datasheet PDF

Part CXA1390AQ
Description S/H and AGC for CCD Camera
Feature CXA1390AQ; CXA1390AQ/AR S/H and AGC for CCD Camera Description The CXA1390AQ/AR are CCD camera's signal process.
Manufacture Sony Corporation
Datasheet
Download CXA1390AQ Datasheet




CXA1390AQ
CXA1390AQ/AR
S/H and AGC for CCD Camera
Description
The CXA1390AQ/AR are CCD camera's signal
processing ICs which extract signals from the CCD
output. These bipolar ICs perform correlated double
sampling. AGC, color separation, high luminance
detection and others. Additionary, these ICs are not
affected by irregular pulses which occure during the
CCD shutter mode.
Featuers
Pin compatible upgraded version of CXA1390Q/R
which can be swapped out while using same
peripheral chips
Almost completely corrects irregular pulses and
their negative affects
Correlated double sampling function alllows for the
suppression of low band noise in the CCD output
AGC amplifier, which has High S/N ratio and wide
gain control range, enhances the camera sensitivity
Output for iris adjustment. High luminance
detection output
Usage of Vg (regulator) output allows for the
formation of IRIS and AGC LOOP which are not
affected by supply voltage functation
Operating Conditions
Supply voltage VCC
4.75 to 5.25
V
Block Diagram and Pin Configuration (Top View)
CXA1390AQ
48 pin QFP (Plastic)
CXA1390AR
48 pin LQFP (Plastic)
Application
S/H and AGC for CCD camera
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings (Ta = 25°C)
Supply voltage
VCC 12 V
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –65 to +150 °C
Allowable power dissipation
PD 600 (QFP) mW
950 (VQFP) mW
(40mm × 40mm, t = 0.8mm with a mounted glass epoxy
substrate)
24 23 22 21 20 19 18 17 16 15 14 13
DET LEVEL 25
AGC CLP 26
AGC OUT 27
OP IN + 28
OP IN – 29
OP OUT 30
AGC CONT 31
AGC MAX 32
AGC SEL 33
XSHP 34
XSHD 35
CLP4 36
SLICE GC
SLICE GC
CLP
SH
XSP3
SH
XSP2
SH
XSP1
CLP1
LPF
CLP
BLK
PBLK
CLP1
LPF
CLP
BLK
PBLK
CLP1
LPF
PBLK
CLP
BLK
12 CSAGC SL
11 CSAGC GC
10 CS OUT
9 CS CCD GC
8 CS CCD SL
7 CS CLP
6 F3 OUT
5 F2 OUT
4 F1 OUT
3 GY OUT
GATE
2 DC OUT
1 XSH1
37 38 39 40 41 42 43 44 45 46 47 48
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E90941A78



CXA1390AQ
Pin Description and Standard Pin voltage
PIn
No. Symbol
Voltage
1 XSH1
34 XSHP
35 XSHD
40 XSP3
41 XSP2
H: 4V and above
L: 1V and below
42 XSP1
48 XSH2
2 DC OUT
1.8 to 2.1V
CXA1390AQ/AR
Equivalent circuit
(VCC = 5V)
Description
1
34
35 130
40
41
42
48
200
High speed pulse input
pin for S/H (active at L)
200
1k
180µA
DC output pin of f1 to f3
2 output black level
3 GY OUT
4 F1 OUT
5 F2 OUT
6 F3 OUT
27 AGC OUT
7 CS CLP
18 IRIS CLP
20 DET CLP
26 AGC CLP
45 F3 CLP
46 F2 CLP
47 F1 CLP
10 CS OUT
17 IRIS OUT
24 DET OUT
Black level
1.8 to 2.1V
2.6 to 3.3V
2.0 to 2.6V
1.9 to 2.6V
2.3 to 2.8V
2.0 to 2.6V
2.0 to 2.6V
2.0 to 2.6V
1.7 to 2.2V
1.7 to 2.0V
1.7 to 2.0V
300
360µA
3
4
5 Signal output pin
6
27
130
300
200µA
7
18
20
Capacitor connecting
26 pin for clamp
45
46
47
Signal output pin
10
17
Signal output pin Vcc
24 fluctuations effect is
minor on DC level
–2–



CXA1390AQ
CXA1390AQ/AR
PIn
No.
Symbol
8 CS CCD SL
Voltage
Equivalent circuit
9 CS CCD GC
11 CSAGC GC
8
9
12 CSAGC SL
11
12
21
(Test mode at 0V)
IRIS LEVEL
21
22
22 IRIS GC
25
31
25 DET LEVEL
32
31 AGC CONT
32 AGC MAX
130
13 CLP1
14 P BLK
15 WND
36 CLP4
13
14
H: 4V and above
L: 1V and below
15
36
130
130
Description
Level adjustment pin of high
luminance detection pin of the
input signal
Gain adjustment pin of input
signal high luminance part
Gain adjustment pin of high
luminance port after AGC
Level adjustment pin of high
luminance detection after AGC
Adjustment pin of IRIS output
weighting (Active at WND = L)
Gain adjustment pin of IRIS
output
Adjustment pin of DET output
weighting (Active at WND = L)
AGC amplifier gain
adjustment pin
AGC amplifier MAX gain
adjustment pin
CLP1 pulse input pin
Active at H (OPB clamp)
Pre BLK pulse input pin
Active at L
Window pulse input pin
Active at L
CLP4 pulse input pin
Active at H
16 VG OUT
2.6 to 3.1V
100µA
Regulator output pin
16 (Used for the formation of
AGC and IRIS loop)
28 OP IN +
29 OP IN –
1 to 3.3V
28
29
130
130
–3–
Operation amplifier non
inverted input pin
Operation amplifier inverted
input pin







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