CMOS Digital Delay Line
CXD101-106Q(1/2) IL08D
C-MOS DIGITAL DELAY LINE
—TOP VIEW— 36 35 34 33 32 31 30 29 28 27 26 25
1 2 DIN0 DIN1 DIN2 DIN3 ...
Description
CXD101-106Q(1/2) IL08D
C-MOS DIGITAL DELAY LINE
—TOP VIEW— 36 35 34 33 32 31 30 29 28 27 26 25
1 2 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 DIN10 DOT0 DOT1 DOT2 DOT3 DOT4 DOT5 DOT6 DOT7 DOT8 DOT9 DOT10 36 35 34 33 32 31 29 28 27 38 37
GND
3
GND
37 38 39 40 41 42 43 44 45 46 47 48
NC VDD NC NC VDD NC
24 23 22 21 20 19 18 17 16 15 14 13
4 5 7 8 9 10 47 48
11 24 25
DOP MODE OEN
SDO
26
14
1 2 3 4 5 6 7 8 9 10 11 12
SCK SIN STB YC LTP DG1 DG2 DG3 SOUT 13
15 16
INPUT CLK DIN0 - DIN10 DOP MODE OEN
; ; ; ; ;
(
TINT SCK SIN STB YC DG1-DG3 LTP CP2 INV OUTPUT DOT0 - DOT10 SDO SOUT TOT ; ; ; ; ; ; ; ; ;
CLOCK DATA DO PULSE H : 14CK DELAY L : 5CK DELAY OUTPUT ENABLE L : DOT0-10 OUTPUT STATUS H : HIGH IMPEDANCE STATUS H : MPU COMMUNICATION MODE MPU SERIAL I/F CLOCK MPU SERIAL DATA IN MPU SERIAL I/F STROBE L : CHROMA, H : Y FOR DIAG FOR DIAG TEST TERMINAL GENERALLY USE : L TEST TERMINAL GENERALLY USE : L
17 20 21 22 23
)
12
TINT 46
39 40
INV CP2
TOT
42
; ; ; ;
DATA STRETCHED DO DATA OUT TO MPU TEST
CXD101-106Q(2/2) PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 PIN NO. 13 14 15 16 17 18 19 20 21 22 23 24 PIN NO. 25 26 27 28 29 30 31 32 33 34 35 36 PIN NO. 37 38 39 40 41 42 43 44 45 46 47 48
I/O I I I I I — I I I I I I
SIGNAL DIN0 DIN1 DIN2 DIN3 DIN4 GND DIN5 DIN6 DIN7 DIN8 DOP TINT
I/O O I I I I — — I I I I I
SIGNAL SOUT SCK SIN STB YC NC VDD LTP DG1 DG2 DG3 MODE
I/O I O O O O — O O O O O O
SIGNAL OEN SDO DOT8 DOT7 DOT6 GND DOT5 DOT4 DOT3 DOT2 DOT1 DOT0
I/...
Similar Datasheet