CY2509

CY2509/10 Spread Aware™, Ten/Eleven Output Zero Delay Buffer Features ■ Spread Aware™ www.DataSheet4U.net ■ Key Specifications Operating voltage: ...............................................3.3 V±10% Operating range: ......................... 40 MHz < fOUT < 140 MHz Cycle-to-cycle jitter: ................................................. <100 ps Output to output skew: ............................................. <100 ps Phase error jitter: ...................................................... <100 ps designed to work with spread spectrum frequency timing generator (SSFTG) reference signals Well suited to both 100- and 133-MHz designs Ten (CY2509) or eleven (CY2510) low-voltage complementary metal oxide semiconductor (LVCMOS) / low-voltage transistortransistor logic (LVTTL) outputs. 50 ps typical peak cycle-to-cycle jitter Single output enable pin for CY2510 version, dual pins on CY2509 devices allow shutting down a portion of the outputs 3.3 V power supply On-chip 25  damping resistors Available in 24-pin thin shrunk small outline package (TSSOP) package Improved tracking skew, but narrower frequency support limit when compared to W132-09B/10B ■ ■ ■ ■ ■ ■ Block Diagram FBIN CLK PLL FBOUT Q0 Q1 Q2 OE0:4 Q3 OE Q4 Q5 OE5:8 Q6 Q7 Q8 Q9 Configuration of these blocks dependent upon specific option being used Cypress Semiconductor Corporation Document Number: 38-07230 Rev. *E 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised July 5, 2011 CY...