CY29351 Datasheet





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CY29351 Datasheet - 9-Output Zero Delay

CY29351   CY29351  

Datasheet: CY29351 datasheet

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Description: PRELIMINARY CY29351 2.5V or 3.3V, 200 M Hz, 9-Output Zero Delay Features ■ ■ ■ Functional Description The C Y29351 is a low voltage high performanc e 200 MHz PLL-based zero delay buffer d esigned for high speed clock distributi on applications. The CY29351 features L VPECL and LVCMOS reference clock inputs and provides 9 outputs partitioned in four banks of one, one, two, and five o utputs. Bank A divides the VCO output b y two or four while the other banks div ide by four or eight per SEL(A:D) setti ngs (Table 3, “Function Table,” on page 3). These dividers allow output to input ratios of 4:1, 2:1, 1:1, 1:2, an d 1:4. Each LVCMOS compatible output ca n drive 50Ω series or parallel terminated transm


Manufacture Part Number Description

Cypress Semiconductor

CY29351

9-Output Zero Delay




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