CY54FCT377T

CY54FCT377T, CY74FCT377T 8-BIT REGISTERS D Function, Pinout, and Drive Compatible With FCT and F Logic D Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions D Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics D Ioff Supports Partial-Power-Down Mode Operation D Matched Rise and Fall Times D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) D Fully Compatible With TTL Input and Output Logic Levels D Clock Enable for Address and Data Synchronization Application D Eight Edge-Triggered D-Type Flip-Flops D CY54FCT377T – 32-mA Output Sink Current – 12-mA Output Source Current D CY74FCT377T – 64-mA Output Sink Current – 32-mA Output Source Current CP CE O4 D4 O7 SCCS023A – MAY 1994 – REVISED OCTOBER 2001 SN74FCT377T . . . Q OR SO PACKAGE (TOP VIEW) CE O0 D0 D1 O1 O2 D2 D3 O3 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 O7 18 D7 17 D6 16 O6 15 O5 14 D5 13 D4 12 O4 11 CP SN54FCT377T . . . L PACKAGE (TOP VIEW) VCC 3 2 1 20 19 D1 4 18 D7 O1 5 17 D6 O2 6 16 O6 D2 7 15 O5 D3 8 14 9 10 11 12 13 D5 O3 D0 GND O0 description The ’FCT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The common buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE) input is low. The register is fully edge triggered. The state of each D input at one setup time before the low-to-high clock transition is tr...