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CY6264 Datasheet

8K x 8 Static RAM

1CY 626 4 PRELIMINARY CY6264 8K x 8 Static RAM Features • 55, 70 ns access times • CMOS for optimum speed/power • Easy memory expansion with CE1, CE2, and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected over 70% when deselected. The CY6264 is packaged in a 450-mil (300-mil body) SOIC. An active LOW write en.

Cypress Semiconductor
CY6264.pdf

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Cypress Semiconductor CY6264 Datasheet
1CY 626 4 PRELIMINARY CY6264 8K x 8 Static RAM Features • 55, 70 ns access times • CMOS for optimum speed/power • Easy memory expansion with CE1, CE2, and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected over 70% when deselected. The CY6264 is packaged in a 450-mil (300-mil body) SOIC. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance sta.





1CY 626 4 PRELIMINARY CY6264 8K x 8 Static RAM Features • 55, 70 ns access times • CMOS for optimum speed/power • Easy memory expansion with CE1, CE2, and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected over 70% when deselected. The CY6264 is packaged in a 450-mil (300-mil body) SOIC. An active LOW write en.

Cypress Semiconductor
CY6264.pdf

Preview
Preview


Preview

Cypress Semiconductor CY6264 Datasheet
1CY 626 4 PRELIMINARY CY6264 8K x 8 Static RAM Features • 55, 70 ns access times • CMOS for optimum speed/power • Easy memory expansion with CE1, CE2, and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected over 70% when deselected. The CY6264 is packaged in a 450-mil (300-mil body) SOIC. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance sta.







 

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