CY74FCT373T

D Function and Pinout Compatible With FCT and F Logic D Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions D Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics D Ioff Supports Partial-Power-Down Mode Operation D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) D Matched Rise and Fall Times D Fully Compatible With TTL Input and Output Logic Levels D 3-State Outputs D CY54FCT373T – 32-mA Output Sink Current – 12-mA Output Source Current D CY74FCT373T – 64-mA Output Sink Current – 32-mA Output Source Current CY54FCT373T, CY74FCT373T 8-BIT LATCHES WITH 3-STATE OUTPUTS SCCS021B – MAY 1994 – REVISED OCTOBER 2001 CY54FCT373T . . . D PACKAGE CY74FCT373T . . . Q OR SO PACKAGE (TOP VIEW) OE O0 D0 D1 O1 O2 D2 D3 O3 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 O7 18 D7 17 D6 16 O6 15 O5 14 D5 13 D4 12 O4 11 LE description The ’FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE) input is low. When OE is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches. These devices are fully specified for partial-power-down applications using Ioff. The Ioff ci...