D Function, Pinout, and Drive Compatible
With FCT and F Logic
D Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times D Fully Compatible With TTL Input and
Output Logic Levels
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Edge-Trigger.
8-BIT REGISTERS
D Function, Pinout, and Drive Compatible
With FCT and F Logic
D Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times D Fully Compatible With TTL Input and
Output Logic Levels
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Edge-Triggered D-Type Inputs D 250-MHz Typical Switching Rate D CY54FCT374T
– 32-mA Output Sink Current
– 12-mA Output Source Current
D CY74FCT374T
– 64-mA Output Sink Current
– 32-mA Output Source Current
D 3-State Outputs
CY54FCT374T, CY74FCT374T 8-BIT REGISTERS
WITH 3-STATE OUTPUTS
SCCS022A – MAY 1994 – REVISED OCTOBER 2001
CY54FCT374T . . . D PACKAGE CY74FCT374T . . . P, Q, OR SO PACKAGE
(TOP VIEW)
OE
O0 D0 D1 O1 O2 D2 D3 O3 GND
1 2 3 4 5 6 7 8 9 10
20 VCC 19 O7 18 D7 17 D6 16 O6 15 O5 14 D5 13 D4 12 O4 11 CP
CY54FCT374T . . . L PACKAGE (TOP VIEW)
D0 O0 OE VCC O7
D1
3 2 1 20 19 4 18
D7
O1 5
17 D6
O2 6
16 O6
D2 7
15 O5
D3
8 14 9 10 11 12 13
D5
O3 GND
CP O4 D4
description
The ’FCT374T devices are high-speed, low-power, octal D-type flip-flops, featuring separate D-type inputs for each flip-flop. These devices have 3-state outputs for bus-oriented applications. A buffered clock (CP) and output-enable (OE) inputs are common to all flip-flops. The eight flip-flops in the ’FCT374.