CY74FCT823T

D Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29823 D Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions D Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics D Ioff Supports Partial-Power-Down Mode Operation D Matched Rise and Fall Times D Fully Compatible With TTL Input and Output Logic Levels D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) D 64-mA Output Sink Current 32-mA Output Source Current D High-Speed Parallel Register With Positive-Edge-Triggered D-Type Flip-Flops D Buffered Common Clock-Enable (EN) and Asynchronous-Clear (CLR) Inputs D 3-State Outputs CY74FCT823T 9-BIT BUS-INTERFACE REGISTER WITH 3-STATE OUTPUTS SCCS069A – OCTOBER 2001 – REVISED NOVEMBER 2001 P, Q, OR SO PACKAGE (TOP VIEW) OE D0 D1 D2 D3 D4 D5 D6 D7 D8 CLR GND 1 2 3 4 5 6 7 8 9 10 11 12 24 VCC 23 Y0 22 Y1 21 Y2 20 Y3 19 Y4 18 Y5 17 Y6 16 Y7 15 Y8 14 EN 13 CP description This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a 9-bit-wide buffered register with clock-enable (EN) and clear (CLR) inputs that are ideal for parity bus interfacing in high-performance microprogrammed systems. It is ideal for use as an output port requiring high IOL/IOH. This device is designed for high-capacitance l...