CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18
18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
Features
Separate Independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 375 MHz clock for high bandwidth ■ 4-Word Burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read an...
