CY7C1356CV25

CY7C1354CV25 CY7C1356CV25 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture Features ■ Pin-compatible with and functionally equivalent to ZBT™ ■ Supports 250-MHz bus operations with zero wait states ■ Available speed grades are 250, 200, and 166 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully registered (inputs and outputs) for pipelined operation ■ Byte write capability ■ Single 2.5 V power supply (VDD) ■ Fast clock-to-output times ❐ 2.8 ns (for 250-MHz device) ■ Clock enable (CEN) pin to suspend operation ■ Synchronous self-timed writes ■ Available in Pb-free 100-pin TQFP package, Pb-free and non Pb-free 119-ball BGA package and 165-ball FBGA package ■ IEEE 1149.1 JTAG-compatible boundary scan ■ Burst capability–linear or interleaved burst order ■ “ZZ” sleep mode option and stop clock option Functi...