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CY7C1372DV25 Datasheet

Part Number CY7C1372DV25
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Datasheet CY7C1372DV25 DatasheetCY7C1372DV25 Datasheet (PDF)

CY7C1370DV25 CY7C1372DV25 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture Features ■ Pin-compatible and functionally equivalent to ZBT™ ■ Supports 200-MHz bus operations with zero wait states ❐ Available speed grades are 200 and 167 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully registered (inputs and outputs) for pipelined operation ■ Byte write capabili.

  CY7C1372DV25   CY7C1372DV25






18-Mbit (512K x 36/1M x 18) Pipelined SRAM

CY7C1370DV25 CY7C1372DV25 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture Features ■ Pin-compatible and functionally equivalent to ZBT™ ■ Supports 200-MHz bus operations with zero wait states ❐ Available speed grades are 200 and 167 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully registered (inputs and outputs) for pipelined operation ■ Byte write capability ■ Single 2.5 V core power supply (VDD) ■ 2.5 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 3.0 ns (for 200-MHz device) ■ Clock enable (CEN) pin to suspend operation ■ Synchronous self-timed writes ■ Available in JEDEC-standard Pb-free 100-pin TQFP, and non Pb-free 165-ball FBGA packages ■ IEEE 1149.1 JTAG-compatible boundary scan ■ Burst capability – linear or interleaved burst order ■ “ZZ” sleep mode option and stop clock option Fun.


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