CY7C1418KV18/CY7C1420KV18
36-Mbit DDR II SRAM Two-Word Burst Architecture
36-Mbit DDR II SRAM Two-Word Burst Architectu...
CY7C1418KV18/CY7C1420KV18
36-Mbit DDR II SRAM Two-Word Burst Architecture
36-Mbit DDR II SRAM Two-Word Burst Architecture
Features
■ 36-Mbit density (2M × 18, 1M × 36) ■ 333 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems ■ Synchronous internally self-timed writes ■ DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH ■ Operates similar to DDR-I device with 1 cycle read latency
when DOFF is asserted LOW ■ 1.8 V core power supply with HSTL inputs and outputs ■ Variable drive HSTL output buffers ■ Expanded HSTL output
voltage (1.4 V to VDD)
❐ Supports both 1.5 V and 1.8 V IO supply ■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm) ■ Offered in both Pb-free and non Pb-free packages ■ JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement
Configurations
CY7C1418KV18 – 2M × 18 CY7C1420KV18 – 1M × 36
Functional Description
The CY7C1418KV18, and CY7C1420KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are...