CY7C1620KV18

CY7C1618KV18/CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture 144-Mbit DDR II SRAM Two-Word Burst Architecture Features ■ 144-Mbit density (8M × 18, 4M × 36) ■ 333 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Synchronous internally self-timed writes ■ DDR II operates with 1.5-cycle read latency when DOFF is asserted high ■ Operates similar to DDR I device with one cycle read latency when DOFF is asserted low ■ 1.8-V core power supply with high-speed transceiver logic (HSTL) inputs and outputs ■ Variable drive HSTL output buffers ■ Expanded HSTL output voltage (1.4 V–VDD) ❐ Supports b...