Buffer. CY7C9915 Datasheet

CY7C9915 Datasheet PDF


Part

CY7C9915

Description

3.3V Programmable Skew Clock Buffer

Manufacture

Cypress Semiconductor

Page 14 Pages
Datasheet
Download CY7C9915 Datasheet


CY7C9915 Datasheet
PRELIMINARY
CY7C9915
3.3V Programmable Skew Clock Buffer
Features
• All output pair skew <100 ps (typical)
• Input Frequency Range: 3.75 MHz to 150 MHz
• Output Frequency Range: 3.75 MHz to 150 MHz
• User-selectable output functions
— Selectable skew to 18 ns
— Inverted and non-inverted
— Operation at 12 and 14 input frequency
— Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
www.DataSheZerto4Uin.pcuotm-to-output delay
• 3.3V power supply
• ± 3.0% Output Duty Cycle Distortion
LVTTL outputs drive 50terminated lines
• Low operating current
• 32-pin PLCC package
• Jitter < 100ps peak-to-peak (< 15 ps RMS)
Block Diagram
TEST
FB
REF
PHASE
FREQ FILTER
DET
FS
VCO AND
TIME UNIT
GENERATOR
4F0
4F1 SELECT
INPUTS
(THREE
3F0 LEVEL)
3F1
2F0
2F1
SKEW
SELECT
MATRIX
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Functional Description
The CY7C9915 RoboClock is a 150-MHz Low-voltage
Programmable Skew Clock Buffer that offers user-selectable
control over system clock functions. This multiple-output clock
driver provides the system integrator with functions necessary
to optimize the timing of high-performance computer systems.
Eight individual drivers, arranged as four pairs of user-control-
lable outputs, can each drive terminated transmission lines
with impedances as low as 50while delivering minimal and
specified output skews and full-swing logic levels (LVTTL).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.42 to 1.6 ns are deter-
mined by the operating frequency with outputs able to skew up
to ±6 time units from their nominal “zero” skew position. The
completely integrated PLL allows external load and trans-
mission line delay effects to be canceled. When this “zero
delay” capability of the LVPSCB is combined with the
selectable output skew functions, the user can create
output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility
minimizes clock distribution difficulty while allowing maximum
system clock speed and flexibility.
Pin Configuration
3F1
4F0
4F1
VCCQ
VCCN4
4Q1
4Q0
GND
GND
4 3 2 1 32 31 30
5 29
6 28
7 27
8 26
9 CY7C9915
10
25
24
11 23
12 22
13 21
14 15 16 17 18 19 20
2F0
GND
1F1
1F0
VCCN1
1Q0
1Q1
GND
GND
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07687 Rev. *A
Revised April 29, 2005

CY7C9915 Datasheet
PRELIMINARY
CY7C9915
Pin Definitions (CY7C9915)
Pin No.
Name
1 REF
17 FB
3 FS
26,27 1F0, 1F1
29,30 2F0, 2F1
4,5 3F0, 3F1
6,7 4F0, 4F1
31 Test
23,24 1Q0, 1Q1
19,20 2Q0, 2Q1
14,15 3Q0, 3Q1
10,11
4Q0, 4Q1
www.DataSheet42U5.com VCCN1
18 VCCN2
16 VCCN3
9 VCCN4
2,8 VCCQ
12,13,21,22, GND
28, 32
I/O
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Power
Power
Power
Power
Power
Ground
Type
LVTTL/LVCMOS
LVTTL
Three-level
Three-level
Three-level
Three-level
Three-level
Three-level
LVTTL
LVTTL
LVTTL
LVTTL
POWER
POWER
POWER
POWER
POWER
POWER
Description
Reference Clock Input
Feedback Clock Input
Three Level Frequency Range Select
Three level function select for 1Q0,1Q1
Three level function select for 2Q0,2Q1
Three level function select for 3Q0,3Q1
Three level function select for 4Q0,4Q1
Three level select for test modes
Output Pair
Output Pair
Output Pair
Output Pair
3.3V Power Supply for output pair 1Q0 and 1Q1.
3.3V Power Supply for output pair 2Q0 and 2Q1.
3.3V Power Supply for output pair 3Q0 and 3Q1.
3.3V Power Supply for output pair 4Q0 and 4Q1.
3.3V Core Power
Ground
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept inputs from the Reference Frequency
(REF) input and the Feedback (FB) input and generate
correction information to control the frequency of the
Voltage-Controlled Oscillator (VCO). These blocks, along with
the VCO, form a Phase-Locked Loop (PLL) that tracks the
incoming REF signal.
Table 1. Frequency Range Select and tU Calculation[1]
fNOM (MHz)
FS[2] Min. Max.
tU = f---N---O----M-1-----×----N---
where N =
Approximate
Frequency (MHz)
At WhicnhstU = 1.0
LOW 15 30
44
22.7
MID 25 50
26
38.5
VCO and Time Unit Generator
HIGH 40 150
16
62.5
The VCO accepts analog control inputs from the PLL filter
block and generates a frequency that is used by the time unit
generator to create discrete time units that are selected in the
skew select matrix. The operational range of the VCO is deter-
mined by the FS control pin. The time unit (tU) is determined
by the operating frequency of the device and the level of the
FS pin as shown in Table 1.
Notes:
Skew Select Matrix
The skew select matrix is comprised of four independent
sections. Each section has two low-skew, high-fanout drivers
(xQ0, xQ1), and two corresponding three-level function select
(xF0, xF1) inputs. Table 2 below shows the nine possible
output functions for each section as determined by the function
select inputs. All times are measured with respect to the REF
input assuming that the output connected to the FB input has
0tU selected.
1.
For all three-state inputs, HIGH indicates a connection
circuitry holds an unconnected input to VCC/2.
to VCC, LOW
indicates
a
connection
to
GND, and
MID indicates
an open
connection. Internal termination
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Document #: 38-07687 Rev. *A
Page 2 of 14


Features Datasheet pdf PRELIMINARY CY7C9915 3.3V Programmable Skew Clock Buffer Features • All out put pair skew <100 ps (typical) • Inp ut Frequency Range: 3.75 MHz to 150 MHz • Output Frequency Range: 3.75 MHz t o 150 MHz • User-selectable output fu nctions — Selectable skew to 18 ns Inverted and non-inverted — Operati on at 1⁄2 and 1⁄4 input frequency Operation at 2x and 4x input frequen cy (input as low as 3.75 MHz) Function al Description The CY7C9915 RoboClock i s a 150-MHz Low-voltage Programmable Sk ew Clock Buffer that offers user-select able control over system clock function s. This multiple-output clock driver pr ovides the system integrator with funct ions necessary to optimize the timing o f high-performance computer systems. Ei ght individual drivers, arranged as fou r pairs of user-controllable outputs, c an each drive terminated transmission l ines with impedances as low as 50Ω wh ile delivering minimal and specified ou tput skews and full-swing logic levels (LVTTL). Each output can be hardwired to one o.
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