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DAC1405D650 Datasheet

Part Number DAC1405D650
Manufacturers IDT
Logo IDT
Description Dual 14-bit DAC
Datasheet DAC1405D650 DatasheetDAC1405D650 Datasheet (PDF)

DAC1405D650 Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating Rev. 05 — 2 July 2012 Product data sheet 1. General description The DAC1405D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 2, 4 or 8 interpolating filters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1405D650 allows the complex I and Q inputs to be converted up from baseband to IF. The mixing frequency is adjusted via a .

  DAC1405D650   DAC1405D650






Part Number DAC1405D650
Manufacturers NXP Semiconductors
Logo NXP Semiconductors
Description Dual 14-bit DAC
Datasheet DAC1405D650 DatasheetDAC1405D650 Datasheet (PDF)

DAC1405D650 Rev. 01 — 4 May 2009 www.DataSheet4U.com Dual 14-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating Product data sheet 1. General description The DAC1405D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 2×, 4× or 8× interpolating filters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1405D650 allows the complex I and Q inputs to be converted up from baseband to IF. The mixing frequency is.

  DAC1405D650   DAC1405D650







Dual 14-bit DAC

DAC1405D650 Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating Rev. 05 — 2 July 2012 Product data sheet 1. General description The DAC1405D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 2, 4 or 8 interpolating filters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1405D650 allows the complex I and Q inputs to be converted up from baseband to IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register. Two modes of operation are available: separate data ports or a single interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. The DAC1405D650 also includes a 2, 4 and 8 clock multiplier which provides the appropriate internal clocks and an internal regulator to adjust the output full-scale current. 2. Features and benefits  Dual 14-bit resolution  650 Msps maximum update rate  IMD3: 80 dBc; fs = 640 Msps; fo = 96 MHz  ACPR: 71 dBc; 2 carriers WCDMA; fs = 614.4 Msps; fo = 96 MHz; PLL on  Selectable 2, 4 or 8 interpolation  Typical 0.95 W power dissipation at 4 filters interpolation  Input data rate up to 160 Msps  Power-down and Sleep modes  Very low noise cap-free integrated PLL  Differential scalable output current from 1.6 mA to 22 m.


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