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DLPC4422 DLP® Display Controller
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Technical Documents
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DLPC4422 DLP® Display Controller
DLPC4422
DLPS074 – FEBRUARY 2017
1 Features
1 Provides Two 30-bit Input Pixel Interfaces or One 60-bit Input Pixel Interface: – YUV, YCrCb, or RGB Data Format – 8, 9 or 10 Bits per Color – Pixel Clock Support Up to 175 MHz for 30-bit and 160 MHz for 60-bit
Supports 24-30 Hz and 47-120 Hz Frame Rates Full Single DLP Controller Support For DMD™s
Up to 1920 Pixels Wide Dual DLP Controller Support For Up to 4K Ultra
High Definition (UHD) Resolution Display Using DLP660TE TRP DMD High-Speed, Low
Voltage Differential Signaling (LVDS) DMD Interface 150 MHz ARM946™ Microprocessor Microprocessor Peripherals – Programmable Pulse-Width Modulation (PWM)
and Capture Timers – Three I2C Ports, Three UART Ports and Three
SSP Ports – One USB 1.1 Slave Port Image Processing – Multiple Image Processing Algorithms – Frame Rate Conversion – Color Coordinate Adjustment – Programmable Color Space Conversion – Programmable Degamma and Splash – Integrated Support for 3-D Display On-Screen Display (OSD) Integrated Clock Generation Circuitry
– Operates on a Single 20 MHz Crystal – Integrated Spread Spectrum Clocking External Memory Support – Parallel Flash for Microprocessor and PWM
Sequence – Optional SRAM 516 Pin Plastic Ball Grid Array Package Supports Lamp, LED, and Laser Hybrid Illumination Systems
2 Applications
4K Ultra High Definition (UHD) Displ...