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DS3104-SE Datasheet

Part Number DS3104-SE
Manufacturers Maxim Integrated Products
Logo Maxim Integrated Products
Description Line Card Timing IC
Datasheet DS3104-SE DatasheetDS3104-SE Datasheet (PDF)

www.DataSheet4U.com Rev: 060507 DS3104-SE Line Card Timing IC with Synchronous Ethernet Support General Description The DS3104-SE is a low-cost, feature-rich timing IC for line cards with synchronous Gigabit Ethernet (GbE), 10-Gigabit Ethernet (10GbE), and Fast Ethernet ports. ITU-T recommendation G.8261 (formerly G.pactiming) specifies that network synchronization can be carried over packet links by synchronizing the bit clock of the physical layer as is currently done on SONET/SDH links. The.

  DS3104-SE   DS3104-SE






Line Card Timing IC

www.DataSheet4U.com Rev: 060507 DS3104-SE Line Card Timing IC with Synchronous Ethernet Support General Description The DS3104-SE is a low-cost, feature-rich timing IC for line cards with synchronous Gigabit Ethernet (GbE), 10-Gigabit Ethernet (10GbE), and Fast Ethernet ports. ITU-T recommendation G.8261 (formerly G.pactiming) specifies that network synchronization can be carried over packet links by synchronizing the bit clock of the physical layer as is currently done on SONET/SDH links. The DS3104-SE enables synchronization in Ethernet line cards in both the transmit and receive directions. In the transmit direction, the device accepts traditional SONET/SDH system clocks such as 19.44MHz from redundant system timing cards and synthesizes frequency-locked xMII clock rates, such as the 125MHz GTX_CLK for GbE GMIIs. Each Ethernet PHY then synthesizes a transmit bit clock that is frequency-locked to the xMII clock, and thus to the system clock and network clock. In the receive direction, each PHY divides down the recovered bit clock to produce the receive xMII clock. The DS3104-SE accepts the xMII clock from any of several Ethernet ports and forwards a frequency-locked system clock, such as 19.44MHz, to the system timing cards. SONET/SDH ports are also supported. Features ♦ Timing Card to Line Card Path ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Two Input Clocks from Master and Slave Timing Cards (LVDS/LVPECL or CMOS/TTL) Optional Frame Sync Inputs and Outputs Continuous Input Clock Quality Monitorin.


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