DS90CR486

DS90CR486 www.ti.com SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013 DS90CR486 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps) Check for Samples: DS90CR486 FEATURES 1 2 Up to 6.384 Gbps Throughput 66MHz to 133MHz Input Clock Support Reduces Cable and Connector Size and Cost Cable Deskew Function DC Balance Reduces ISI Distortion For Point-to-Point Backplane or Cable Applications Low Power, 890 mW Typ at 133MHz Flow through Pinout for Easy PCB Design +3.3V Supply Voltage 100-pin TQFP Package Conforms to TIA/EIA-644-A-2001 LVDS Standard DESCRIPTION The DS90CR486 receiver converts eight Low Voltage Differential Signaling (LVDS) data streams back into 48 bits of LVCMOS/LVTTL data. Using a 133MHz clock, the data throughput is 6.384Gbit/s (798Mbytes/s). The multiplexing of data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 48-bit wide data and one clock, up to 98 conductors are required. With this Channel Link chipset as few as 19 conductors (8 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides an 80% reduction in interconnect width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor. The DS90CR486 deserializer is improved over prior generations of Channel Link devices a...