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EDI2AG272128V-D1 Datasheet

Part Number EDI2AG272128V-D1
Manufacturers White Electronic
Logo White Electronic
Description 2 Megabyte Sync/Sync Burst
Datasheet EDI2AG272128V-D1 DatasheetEDI2AG272128V-D1 Datasheet (PDF)

www.DataSheet4U.com White Electronic Designs EDI2AG272128V-D1 ADVANCED* 2 Megabyte Sync/Sync Burst, Small Outline DIMM FEATURES 2x128Kx72 Synchronous, Synchronous Burst Flow-Through Architecture Linear Burst Mode Clock Controlled Registered Bank Enables (E1#, E2#) Clock Controlled Byte Write Mode Enable (BWE#) Clock Controlled Byte Write Enables (BW1# - BW8#) Clock Controlled Registered Address Clock Controlled Registered Global Write (GW#) Aysnchronous Output Enable (G#) Internally self-time.

  EDI2AG272128V-D1   EDI2AG272128V-D1






2 Megabyte Sync/Sync Burst

www.DataSheet4U.com White Electronic Designs EDI2AG272128V-D1 ADVANCED* 2 Megabyte Sync/Sync Burst, Small Outline DIMM FEATURES 2x128Kx72 Synchronous, Synchronous Burst Flow-Through Architecture Linear Burst Mode Clock Controlled Registered Bank Enables (E1#, E2#) Clock Controlled Byte Write Mode Enable (BWE#) Clock Controlled Byte Write Enables (BW1# - BW8#) Clock Controlled Registered Address Clock Controlled Registered Global Write (GW#) Aysnchronous Output Enable (G#) Internally self-timed Write Gold Lead Finish 3.3V ± 10% Operation Access Speed(s): TKHQV=8.5, 9, 10, 12ns Common Data I/O High Capacitance (30pf) drive, at rated Access Speed Single total array Clock Multiple Vcc and Gnd The EDI2AG272128VxxD1 is a Synchronous/Synchronous Burst SRAM, 72 position DIMM (144 contacts) Module, organized as 2x128Kx72. The Module con tains four (4) Synchronous Burst Ram Devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The module architecture is defined as a Sync/Sync Burst, Flow-Through, with support for linear burst. This module provides High Performance, 2-1-1-1 accesses when used in Burst Mode, and used as a Synchronous Only Mode, provides a high performance cost advantage over BiCMOS aysnchronous device architectures. Synchronous Only operations are performed via strapping ADSC# Low, and ADSP#/ADV# High, which provides for Ultra Fast Accesses in Read Mode while providing for internally self-timed Early Writes. Synchronous/S.


2006-11-30 : AT1310    AT1312A    AT1312B    AT1312C    AT1313    AT1314    AT1362A    AT1362B    AT1366    AT1366B   


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