EDJ4208EFBG-L

4Gb: x8, x16 DDR3L-RS SDRAM Description DDR3L-RS SDRAM EDJ4208EFBG-L – 64 Meg x 8 x 8 banks EDJ4216EFBG-L – 32 Meg x 16 x 8 banks Description The 1.35V DDR3L-RS SDRAM device is a low-voltage version of the DDR3 (1.5V) SDRAM. Refer to the DDR3 (1.5V) SDRAM data sheet specifications when running in 1.5V-compatible mode. Features VDD = VDDQ = 1.35V (1.283–1.45V) Backward compatible to VDD = VDDQ = 1.5V ±0.075V – Supports DDR3L devices to be backward compatible in 1.5V applications Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (CK, CK#) 8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Programmable CAS (READ) latency (CL) Programmable posted CAS additive latency (AL) Programmable CAS (WRITE) latency (CWL) Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) Selectable BC4 or BL8 on-the-fly (OTF) Self refresh mode Programmable partial-array self refresh (PASR) Reduced self refresh current – IDD6: 2.2mA (TYP) at 25ºC TC of 0°C to +95°C – 64ms, 8192-cycle refresh at 0°C to +85°C – 32ms at +85°C to +95°C Self refresh temperature (SRT) Automatic self refresh (ASR) Write leveling Multipurpose register Output driver calibration Options Configuration – 512 Meg x 8 – 256 Meg x 16 FBGA package (Pb-free) – x8 – 78-ball (9mm x 10.6mm) Rev. F FBGA package (Pb-free) – x16 – 96-ball FBGA (9mm x 13.5mm) Rev. F Timin...