EDS1232CABB

PRELIMINARY DATA SHEET 128M bits SDRAM EDS1232CABB, EDS1232CATA (4M words × 32 bits) Description The EDS1232CA is a 128M bits SDRAM organized as 1,048,576 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. They are packaged in 90-ball FBGA, 86-pin plastic TSOP (II). Features 2.5V power supply Clock frequency: 133MHz (max.) Single pulsed /RAS ×32 organization 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length (BL): 1, 2, 4, 8 and full page 2 variations of burst sequence  Sequential (BL = 1, 2, 4, 8)  Interleave (BL = 1, 2, 4, 8) Programmable /CAS latency (CL): 2, 3 Byte control by DQM Refresh cycles: 4096 refresh cycles/64ms 2 variations of refresh  Auto refresh  Self refresh FBGA package is lead free solder (Sn-Ag-Cu) Document No. E0247E40 (Ver. 4.0) Date Published July 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2002 EDS1232CABB, EDS1232CATA Ordering Information Part number EDS1232CABB-75-E EDS1232CABB-1A-E EDS1232CABB-75L-E EDS1232CABB-1AL-E EDS1232CATA-75 EDS1232CATA-1A EDS1232CATA-75L EDS1232CATA-1AL 2.5V 4M × 32 4 Supply voltage 2.5V Organization (words × bits) Internal Banks 4M × 32 4 Clock frequency MHz (max.) 133 100 133 100 133 100 133 100 /CAS latency 3 2, 3 3 2, 3 3 2, 3 3 2, 3 86-pin plastic TSOP (II) Package 90-ball FBGA Part Number E D S 12 32 C A BB - 7...