DRAM. EM484M3244VBE Datasheet

EM484M3244VBE Datasheet PDF

Part EM484M3244VBE
Description 128Mb Synchronous DRAM
Feature eorex Revision History Revision 0.1 (Dec. 2013) - First release EM484M3244VBE Dec. 2013 www.eorex.
Manufacture Eorex
Datasheet
Download EM484M3244VBE Datasheet

eorex Revision History Revision 0.1 (Dec. 2013) - First rele EM484M3244VBE Datasheet




EM484M3244VBE
eorex
Revision History
Revision 0.1 (Dec. 2013)
- First release
EM484M3244VBE
Dec. 2013
www.eorex.com
1/18



EM484M3244VBE
eorex
EM484M3244VBE
128Mb (1M4Bank32) Synchronous DRAM
Features
Fully Synchronous to Positive Clock Edge
Single 3.3V 0.3V Power Supply
LVTTL Compatible with Multiplexed Address
Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
Programmable CAS Latency (C/L) - 2 or 3
Data Mask (DQM) for Read / Write Masking
Programmable Wrap Sequence
Sequential (B/L = 1/2/4/8/full Page)
Interleave (B/L = 1/2/4/8)
Burst Read with Single-bit Write Operation
All Inputs are Sampled at the Rising Edge of
the System Clock
Auto Refresh and Self Refresh
4,096 Refresh Cycles / 64ms (15.625us)
Description
The EM484M3244VBE is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
1Meg words x 4 banks by 32 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 128Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages: TFBGA-90B(13mmx8mm).
Ordering Information
Part No
EM484M3244VBE-75F
EM484M3244VBE-75FE
Organization
4M X 32
4M X 32
Max. Freq
133MHz @CL3
133MHz @CL3
Package
TFBGA -90B
TFBGA -90B
Grade
Commercial
Extend temp.
Pb
Free
Free
* EOREX reserves the right to change products or specification without notice.
Dec. 2013
www.eorex.com
2/18




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