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EPM7256E Datasheet

Part Number EPM7256E
Manufacturers Altera
Logo Altera
Description Programmable Logic
Datasheet EPM7256E DatasheetEPM7256E Datasheet (PDF)

  EPM7256E   EPM7256E
September 2005, ver. 6.7 ® MAX 7000 Programmable Logic Device Family Data Sheet Features... f ■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture ■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532 ■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices ■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells ■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) ■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect) ■ PCI-compliant devices available For information on in-system programmable 3.3-V MAX 7000A or 2.5-V MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic De.






Part Number EPM7256B
Manufacturers Altera Corporation
Logo Altera Corporation
Description (EPM7000B) Programmable Logic Device
Datasheet EPM7256E DatasheetEPM7256B Datasheet (PDF)

  EPM7256E   EPM7256E
www.DataSheet4U.com MAX 7000B ® Programmable Logic Device Data Sheet September 2003, ver. 3.4 Features... ■ ■ High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) – Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V MAX 7000A device families – High-density PLDs ranging from 600 to 10,000 usable gates – 3.5-ns pin-to-pin logic delays with counter frequencies in excess of 303.0 MHz Advanced 2.5-V in-system programmability (ISP) – Programs through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – Enhanced ISP algorithm.






Part Number EPM7256AE
Manufacturers Altera Corporation
Logo Altera Corporation
Description Programmable Logic Device
Datasheet EPM7256E DatasheetEPM7256AE Datasheet (PDF)

  EPM7256E   EPM7256E
MAX 7000A ® Includes MAX 7000AE Programmable Logic Device Data Sheet October 2002, ver. 4.3 Features... ■ ■ ■ ■ ■ ■ ■ ■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532 – EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532 Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 Supports JEDEC Jam S.






Programmable Logic

September 2005, ver. 6.7 ® MAX 7000 Programmable Logic Device Family Data Sheet Features... f ■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture ■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532 ■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices ■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells ■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) ■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect) ■ PCI-compliant devices available For information on in-system programmable 3.3-V MAX 7000A or 2.5-V MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet. Table 1. MAX 7000 Device Features Feature EPM7032 Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tFSU (ns) tCO1 (ns) fCNT (MHz) 600 32 2 36 6 5 2.5 4 151.5 EPM7064 1,250 64 4 68 6 5 2.5 4 151.5 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E 1,800 2,500 3,200 3,750 5,000 96 128 160 192 256 6 8 10 12 16 76 100 104 124 164 7.5 6 3 4.5 125.0 7.5 6 3 4.5 125.0 10 7 3 5 100.0 12 7 3 6 90.9 12 7 3 6 90.9 Altera Corporation DS-M.



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