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FIN12AC Datasheet

Part Number FIN12AC
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description uSerDes Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer
Datasheet FIN12AC DatasheetFIN12AC Datasheet (PDF)

  FIN12AC   FIN12AC
FIN12AC µSerDes™ Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges December 2006 FIN12AC µSerDes™ Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Features ■ Low power consumption ■ Fairchild proprietary low-power CTL interface ■ LVCMOS parallel I/O interface: tm Description The FIN12AC is a 12-bit serializer capable of running a parallel frequency range between 5MHz and 40MHz. The frequency range is selected by the S1 and S2 control signals. The bi-directional data flow is controlled through use of a direction (DIRI) control pin. The devices can be configured to operate in a unidirectional mode only by hardwiring the DIRI pin. An internal PhaseLocked Loop (PLL) generates the required bit clock frequency for transfer across the serial link. Options exist for dual or single PLL operation, dependent upon system operational parameters. The device has been designed for low power operation and utilizes Fairch.






uSerDes Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer

FIN12AC µSerDes™ Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges December 2006 FIN12AC µSerDes™ Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Features ■ Low power consumption ■ Fairchild proprietary low-power CTL interface ■ LVCMOS parallel I/O interface: tm Description The FIN12AC is a 12-bit serializer capable of running a parallel frequency range between 5MHz and 40MHz. The frequency range is selected by the S1 and S2 control signals. The bi-directional data flow is controlled through use of a direction (DIRI) control pin. The devices can be configured to operate in a unidirectional mode only by hardwiring the DIRI pin. An internal PhaseLocked Loop (PLL) generates the required bit clock frequency for transfer across the serial link. Options exist for dual or single PLL operation, dependent upon system operational parameters. The device has been designed for low power operation and utilizes Fairchild proprietary low-power control Current Transistor Logic (CTL) interface. The device also supports an ultra low power powerdown mode for conserving power in battery-operated applications. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ – 2mA source / sink current – Over-voltage tolerant control signals Parallel I/O power supply (VDDP) range between 1.65V and 3.6V Analog power supply range of 2.5V to 3.05V Multi-mode operation allows for a single device to operate as Serializer or Deserializer Internal PLL with no exter.



2007-05-29 : FES16FT    FES16GT    FES16HT    FFP08H60S    FIN12AC    FLZ2V2    FLZ2Vx    FLZ3Vx    FLZ4Vx    FLZ5Vx   


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