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GVT71256ZC36 Datasheet

Part Number GVT71256ZC36
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description (GVT7xxxx) 256Kx36/512Kx18 Pipelined SRAM With Nobltm Architecture
Datasheet GVT71256ZC36 DatasheetGVT71256ZC36 Datasheet (PDF)

( DataSheet : www.DataSheet4U.com ) CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 166, 133, 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% and +5% power supply VCC • Separate VCCQ for 3.3V or 2.5V I/O • Single WEN (Read/Write) control pin • .

  GVT71256ZC36   GVT71256ZC36






(GVT7xxxx) 256Kx36/512Kx18 Pipelined SRAM With Nobltm Architecture

( DataSheet : www.DataSheet4U.com ) CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 166, 133, 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% and +5% power supply VCC • Separate VCCQ for 3.3V or 2.5V I/O • Single WEN (Read/Write) control pin • Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications • Interleaved or linear four-word burst capability • Individual byte Write (BWa–BWd) control (may be tied LOW) • CEN pin to enable clock and suspend operations • Three chip enables for simple depth expansion •Automatic power-down feature available using ZZ mode or CE select • JTAG boundary scan • Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid Array), and 100-pin TQFP packages inputs include all addresses, all data inputs, depth-expansion Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD), Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc, and BWd), and Read-Write Control (WEN). BWc and BWd apply to CY7C1354A/GVT71256ZC36 only. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later, its associated data occurs, either Read or Write. A clock enable (CEN) pin allows operation of the CY7C1354A/GVT71256ZC36/CY7C1356A/GVT71512ZC.


2006-04-13 : PE-68517L    PE-68531G    PE-68532G    PE-68538G    PE-68537G    PE-68515L    87CK38N    QQW343Sxxxx    SES5002    SES5003   


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