GVT71512ZC18

( DataSheet : www.DataSheet4U.com ) CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture Features Zero Bus Latency, no dead cycles between Write and Read cycles Fast clock speed: 200, 166, 133, 100 MHz Fast access time: 3.2, 3.6, 4.2, 5.0 ns Internally synchronized registered outputs eliminate the need to control OE Single 3.3V –5% and +5% power supply VCC Separate VCCQ for 3.3V or 2.5V I/O Single WEN (Read/Write) control pin Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications Interleaved or linear four-word burst capability Individual byte Write (BWa–BWd) control (may be tied LOW) CEN pin to enable clock and suspend operations Three chip enables for simple depth expansion Automatic power-down feature available using ZZ mode or CE select JTAG boundary scan Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid Array), and 100-pin TQFP packages inputs include all addresses, all data inputs, depth-expansion Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD), Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc, and BWd), and Read-Write Control (WEN). BWc and BWd apply to CY7C1354A/GVT71256ZC36 only. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later, its associated data occurs, either Read or Write. A clock enable (CEN) pin allows operation of the CY7C1354A/GVT71256ZC36/CY7C1356A/GVT71512ZC...