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H5TQ1G63BFR-xxC Datasheet

Part Number H5TQ1G63BFR-xxC
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 1Gb DDR3 SDRAM
Datasheet H5TQ1G63BFR-xxC DatasheetH5TQ1G63BFR-xxC Datasheet (PDF)

1Gb DDR3 SDRAM 1Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ1G43BFR-xxC H5TQ1G83BFR-xxC H5TQ1G63BFR-xxC http://www.DataSheet4U.com/ *Hynix Semiconductor reserves the right to change products or specifications without notice Rev. 1.0 / Dec. 2009 1 Revision History Revision No. 0.1 0.2 0.3 0.4 1.0 History Preliminary Initial Release Added IDD Spec Package Dimension Notation change - No Physical change Updated IDD Specification JEDEC Update Draft Date Sep. 2008 Jan. 2009 Apr. 2009.

  H5TQ1G63BFR-xxC   H5TQ1G63BFR-xxC






1Gb DDR3 SDRAM

1Gb DDR3 SDRAM 1Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ1G43BFR-xxC H5TQ1G83BFR-xxC H5TQ1G63BFR-xxC http://www.DataSheet4U.com/ *Hynix Semiconductor reserves the right to change products or specifications without notice Rev. 1.0 / Dec. 2009 1 Revision History Revision No. 0.1 0.2 0.3 0.4 1.0 History Preliminary Initial Release Added IDD Spec Package Dimension Notation change - No Physical change Updated IDD Specification JEDEC Update Draft Date Sep. 2008 Jan. 2009 Apr. 2009 Apr. 2009 Dec. 2009 Remark Preliminary http://www.DataSheet4U.com/ Rev. 1.0 / Dec. 2009 2 Description The H5TQ1G43BFR-xxC, H5TQ1G83BFR-xxC and H5tQ1G63BFR-xxC are a 1,073,741,824-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES • VDD=VDDQ=1.5V +/- 0.075V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM ma.


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