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H5TQ2G43BFR-xxC Datasheet

Part Number H5TQ2G43BFR-xxC
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 2Gb DDR3 SDRAM
Datasheet H5TQ2G43BFR-xxC DatasheetH5TQ2G43BFR-xxC Datasheet (PDF)

2Gb DDR3 SDRAM www.DataSheet4U.com 2Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ2G43BFR-xxC H5TQ2G83BFR-xxC H5TQ2G63BFR-xxC * Hynix Semiconductor reserves the right to change products or specifications without notice. Rev. 0.2 / Feb. 2010 1 www.DataSheet4U.com Revision History Revision No. 0.1 0.2 History Initial Release Added IDD Specification Draft Date Dec. 2009 Feb. 2010 Remark Rev. 0.2 / Feb. 2010 2 www.DataSheet4U.com Description The H5TQ2G43BFR-xxC, H5TQ2G83BFR-xxC.

  H5TQ2G43BFR-xxC   H5TQ2G43BFR-xxC






2Gb DDR3 SDRAM

2Gb DDR3 SDRAM www.DataSheet4U.com 2Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ2G43BFR-xxC H5TQ2G83BFR-xxC H5TQ2G63BFR-xxC * Hynix Semiconductor reserves the right to change products or specifications without notice. Rev. 0.2 / Feb. 2010 1 www.DataSheet4U.com Revision History Revision No. 0.1 0.2 History Initial Release Added IDD Specification Draft Date Dec. 2009 Feb. 2010 Remark Rev. 0.2 / Feb. 2010 2 www.DataSheet4U.com Description The H5TQ2G43BFR-xxC, H5TQ2G83BFR-xxC and H5TQ2G63BFR-xxC are a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES • VDD=VDDQ=1.5V +/- 0.075V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data.


2010-03-16 : 2SMES-01    EE-SX198    EE-SX199    H5TQ2G43AFR-xxC    H5TQ2G83AFR-xxC    H5TQ2G43BFR-xxC    H5TQ2G83BFR-xxC    H5TQ4G43AMR-xxC    H5TQ4G83AMR-xxC    HMT112R7AFP8C   


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