H5TQ2G83CFR-xxC

Preliminary 2Gb DDR3 SDRAM 2Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ2G43CFR-xxC H5TQ2G83CFR-xxC http://www.DataSheet4U.net/ * Hynix Semiconductor reserves the right to change products or specifications without notice. Rev. 0.01 / Nov. 2010 1 datasheet pdf - http://www.DataSheet4U.net/ Preliminary Revision History Revision No. 0.01 History Preliminary version release Draft Date Nov. 2010 Remark Preliminary http://www.DataSheet4U.net/ Rev. 0.01 / Nov. 2010 2 datasheet pdf - http://www.DataSheet4U.net/ Preliminary Description The H5TQ2G43CFR-xxC, H5TQ2G83CFR-xxC are a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES VDD=VDDQ=1.5V +/- 0.075V Fully differential clock inputs (CK, CK) operation Differential Data Strobe (DQS, DQS) BL switch on the fly 8banks Average Refresh Cycle (Tcase of 0 oC~ 95 oC) On chip DLL align DQ, DQS and DQS transition with CK  - 7.8 ...