4Gb DDR3 SDRAM
4Gb DDR3 SDRAM
Lead-Free&Halogen-Free (RoHS Compliant)
H5TQ4G43AFR-xxC H5TQ4G83AFR-xxC H5TQ4G63AFR-xxC
...
4Gb DDR3 SDRAM
4Gb DDR3 SDRAM
Lead-Free&Halogen-Free (RoHS Compliant)
H5TQ4G43AFR-xxC H5TQ4G83AFR-xxC H5TQ4G63AFR-xxC
* SK hynix reserves the right to change products or specifications without notice.
Rev. 1.0 / Apr. 2013 1
Free Datasheet http://www.datasheet4u.com/
Revision History
Revision No. 0.1 1.0 History Initial Release 1.0 version release Draft Date Oct. 2012 Apr. 2013 Remark
Rev. 1.0 / Apr. 2013
2
Free Datasheet http://www.datasheet4u.com/
Description
The H5TQ4G43AFR-xxC, H5TQ4G83AFR-xxC and H5TQ4G63AFR-xxC are a 4Gb
CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
VDD=VDDQ=1.5V +/- 0.075V Fully differential clock inputs (CK, CK) operation 8banks Average Refresh Cycle (Tcase of 0 oC~ 95 oC) Differential Data Strobe (DQS, DQS) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC On chip DLL align DQ, DQS and DQS transition with CK transition JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16 ...