MC74HC125A, MC74HC126A
Quad 3-State Noninverting Buffers
High−Performance Silicon−Gate CMOS
The MC74HC125A and MC74HC1...
MC74HC125A, MC74HC126A
Quad 3-State Noninverting Buffers
High−Performance Silicon−Gate
CMOS
The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be used with 3−state memory address drivers, clock drivers, and other bus−oriented systems. The devices have four separate output enables that are active−low (HC125A) or active−high (HC126A).
Features
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to
CMOS, NMOS, and TTL Operating
Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of
CMOS Devices In Compliance with the JEDEC Standard No. 7 A Requirements Chip Complexity: 72 FETs or 18 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
LOGIC DIAGRAM
HC125A Active−Low Output Enables
HC126A Active−High Output Enables
A1
2
3 Y1
A1
2
3
Y1
OE1
1
5 A2
OE1
1
6
5
Y2
A2
6 Y2
OE2
4
9 A3
OE2
4
8 Y3
A3
9
8
Y3
OE3
10
12 A4
13 OE4
OE3
10
11
12
Y4
A4
13 OE4
PIN 14 = VCC PIN 7 = GND
11 Y4
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 15
http://onsemi.com
SOIC−14 NB D SUFFIX ...