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HCS374MS Datasheet

Part Number HCS374MS
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description Radiation Hardened Octal D-Type Flip-Flop/ Three-State/ Positive Edge Triggered
Datasheet HCS374MS DatasheetHCS374MS Datasheet (PDF)

HCS374MS September 1995 Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered Pinouts 20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T20 TOP VIEW OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 1 2 3 4 5 6 7 8 9 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP Features • • • • • • • • • • • • 3 Micron Radiation Hardened SOS CMOS Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/.

  HCS374MS   HCS374MS






Radiation Hardened Octal D-Type Flip-Flop/ Three-State/ Positive Edge Triggered

HCS374MS September 1995 Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered Pinouts 20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T20 TOP VIEW OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 1 2 3 4 5 6 7 8 9 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP Features • • • • • • • • • • • • 3 Micron Radiation Hardened SOS CMOS Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/BitDay (Typ) Dose Rate Survivability: >1 x 1012 RAD (Si)/s Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse Latch-Up Free Under Any Conditions Fanout (Over Temperature Range) - Bus Driver Outputs - 15 LSTTL Loads Military Temperature Range: -55oC to +125oC Significant Power Reduction Compared to LSTTL ICs DC Operating Voltage Range: 4.5V to 5.5V Input Logic Levels - VIL = 0.3 VCC Max - VIH = 0.7 VCC Min Input Current Levels Ii ≤ 5µA at VOL, VOH GND 10 • Description The Intersil HCS374MS is a Radiation Hardened non-inverting octal D-type, positive edge triggered flip-flop with three-stateable outputs. The HCS374MS utilizes advanced CMOS/SOS technology. The eight flip-flops enter data into their registers on the LOW-to-HIGH transition of the clock (CP). Data is also transferred to the outputs during this transition. The output enable (OE) controls the three-state outputs and is independent of the register operation. When the output enable is high, the outputs are in the high impedance state. Th.


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