HD74HC195

HD74HC195 4-bit Parallel-Access Shift Register REJ03D0590–0200 (Previous ADE-205-467) Rev.2.00 Jan 31, 2006 Description This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; shift from QA towards QD. Parallel loading is accomplished by applying the four bits of data, and taking the Shift/Load control Input low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the Shift/Load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K or toggle flip-flop as shown in the function table. Features High Speed Operation: tpd (Clock to Q) = 13 ns typ (CL = 50 pF) High Output Current: Fanout ...