Quad. S-R Latches
HD74HC279
Quad. S–R Latches
Description
The latch is ideally suited for use as temporary stage for binary information p...
HD74HC279
Quad. S–R Latches
Description
The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established. And when both inputs are low, output is high, but this high level are uncontinuance, if either of input goes high.
Features
High Speed Operation: tpd (S to Q) = 10 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating
Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)
Function Table
Input S* H L H L H : L : Q0 : Notes:
2
Output R H H L L Q Q0 H L H*1
High level Low level The level of Q respectively, before the indicated steady-state input conditions were established. 1. It is unpredictable, if S or R goes High. 2. As to latches which has two S inputs. H: Both of S inputs are high. L: Either or both of S inputs are low.
HD74HC279
Pin Arrangement
1R 1S1 1S2 1Q 2R 2S 2Q GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 4S 4R 4Q 3S2 3S1 3R 3Q
(Top view)
Logic Diagram (1/2)
R
S1 S2 Q
R
S
Q
2
HD74HC279
DC Characteristics
Ta = 25°C Item Input
voltage Symbol VIH Ta = –40 to +85°C Max — — — 0.5 1.35 1.8 — — — — — 0.1 0.1 0.1 0.33 0.33 ±1.0 20 µA µA I OL = 4 mA I OL = 5.2 mA Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = –4 mA I OH = –5.2 mA...