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HDMP-0480 Datasheet

Part Number HDMP-0480
Manufacturers Hewlett-Packard
Logo Hewlett-Packard
Description Octal Cell Port Bypass Circuit without Clock and Data Recovery
Datasheet HDMP-0480 DatasheetHDMP-0480 Datasheet (PDF)

www.DataSheet4U.com Agilent HDMP-0480 Octal Cell Port Bypass Circuit without Clock and Data Recovery Data Sheet Features • Supports 1.0625 GBd fibre channel operation • Supports 1.25 GBd gigabit Ethernet (GE) operation • Octal cell PBC in one package • Valid amplitude detection on FM_NODE[7] input • Equalizers on all inputs • High speed LVPECL I/O • Buffered Line Logic (BLL) outputs (no external bias resistors required) • 0.76 W typical power at Vcc=3.3V • 64 Pin, 10 mm, low cost plastic QFP pa.

  HDMP-0480   HDMP-0480






Part Number HDMP-0482
Manufacturers Hewlett-Packard
Logo Hewlett-Packard
Description Octal Cell Port Bypass Circuit
Datasheet HDMP-0480 DatasheetHDMP-0482 Datasheet (PDF)

www.DataSheet4U.com Agilent HDMP-0482 Octal Cell Port Bypass Circuit with CDR and Data Valid Detection Data Sheet Features • Supports 1.0625 GBd fibre channel operation • Supports 1.25 GBd Gigabit Ethernet (GE) operation • Octal cell PBC/CDR in one package • CDR location determined by choice of cable input/output • Amplitude valid detection on FM_NODE[7] input • Data valid detection on FM_NODE[0] input – Run length violation detection – Comma detection – Configurable for both singleframe and mu.

  HDMP-0480   HDMP-0480







Octal Cell Port Bypass Circuit without Clock and Data Recovery

www.DataSheet4U.com Agilent HDMP-0480 Octal Cell Port Bypass Circuit without Clock and Data Recovery Data Sheet Features • Supports 1.0625 GBd fibre channel operation • Supports 1.25 GBd gigabit Ethernet (GE) operation • Octal cell PBC in one package • Valid amplitude detection on FM_NODE[7] input • Equalizers on all inputs • High speed LVPECL I/O • Buffered Line Logic (BLL) outputs (no external bias resistors required) • 0.76 W typical power at Vcc=3.3V • 64 Pin, 10 mm, low cost plastic QFP package Applications • RAID, JBOD, BTS cabinets • Four 2:1 muxes • Four 1:2 buffers • 1 = > N gigabit serial buffer • N = > 1 gigabit serial mux Description The HDMP-0480 is an Octal Cell Port Bypass Circuit (PBC). This device minimizes part count, cost and jitter accumulation. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system. A Port Bypass Circuit (PBC) consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: “disk in loop” and “disk by-passed”. When the “disk in loop” mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0480’s TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC’s (e.g. an HDMP-1636A) Rx± differential input pins. Data from the Disk Drive Transce.


2006-12-28 : AB32    ADCS-1120    ADCS-2120    ADCS-1121    ADL5530    ADS8482    AMG24064A    ANO11ON    ANO12ON    ANO13ON   


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