HEF40194B

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF40194B MSI 4-bit bidirectional universal shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 4-bit bidirectional universal shift register DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), and four buffered parallel outputs (O0 to O3). When LOW, MR resets all stages and forces O0 to O3 LOW, overriding all other input conditions. When MR is HIGH, the operation mode is controlled by S0 and S1 as shown in the function table. HEF40194B MSI Serial and parallel operation are edge-triggered on the LOW to HIGH transition of CP. The inputs at which the data are to be entered and S0, S1 must be stable for a set-up time before the LOW to HIGH transition of CP. Fig.2 Pinning diagram. HEF40194BP(N): 16-lead DIL; plastic (SOT38-1) HEF40194BD(F): HEF40194BT(D): 16-lead DIL; ceramic (cerdip) (SOT74) Fig.1 Functional diagram. 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING S0, S1 P0 to P3 DSR DSL CP MR O0 to O3 mode control in...