HEF4031B

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4031B MSI 64-stage static shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 64-stage static shift register DESCRIPTION The HEF4031B is an edge-triggered 64-stage static shift register with two serial data inputs (DA, DB), a data select input A/B, a clock input (CP), a buffered clock output (CO), and buffered outputs from the 64th bit position (O63, O63). The output O63 is capable of driving one TTL load. Data from DA or DB, as determined by the state of A/B, is shifted into the first shift register position and all the data in HEF4031B MSI the register is shifted one position to the right on the LOW to HIGH transition of CP. DA is selected by a LOW, and DB by a HIGH on A/B. Registers can be cascaded either by connecting all CP inputs together or by driving CP of the most right-hand register with the system clock and connecting CO to CP of the preceding register. When the second technique is used in the recirculating mode, a flip-flop must be used to store O63 of the most right-hand register until the most left-hand register is clocked. Fig.1 Functional diagram. PINNING DA, DB A/B CP CO O63 O63 data inputs data select input clock input (LOW to HIGH edge-triggered) buffered clock...