HEF4040B

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4040B MSI 12-stage binary counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 12-stage binary counter DESCRIPTION The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. HEF4040B MSI Fig.1 Functional diagram. PINNING CP MR O0 to O11 clock input (HIGH to LOW edge-triggered) master reset input (active HIGH) parallel outputs APPLICATION INFORMATION Some examples of applications for the HEF4040B are: Frequency dividing circuits Time delay circuits Fig.2 Pinning diagram. Control counters FAMILY DATA, IDD LIMITS category MSI HEF4040BP(N): HEF4040BD(F): HEF4040BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America See Family Specifications January 1995 2 Philips Semiconductors Pro...