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HEF4104B Datasheet

Part Number HEF4104B
Manufacturers NXP
Logo NXP
Description Quadruple low to high voltage translator with 3-state outputs
Datasheet HEF4104B DatasheetHEF4104B Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4104B MSI Quadruple low to high voltage translator with 3-state outputs Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple low to high voltage translator with 3-state outputs DESCRIPTION The HEF4104B quadr.

  HEF4104B   HEF4104B






Part Number HEF4104B
Manufacturers nexperia
Logo nexperia
Description Quad low-to-high voltage translator
Datasheet HEF4104B DatasheetHEF4104B Datasheet (PDF)

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  HEF4104B   HEF4104B







Quadruple low to high voltage translator with 3-state outputs

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4104B MSI Quadruple low to high voltage translator with 3-state outputs Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple low to high voltage translator with 3-state outputs DESCRIPTION The HEF4104B quadruple low voltage to high voltage translator with 3-state outputs provides the capability of interfacing low voltage circuits to high voltage circuits, such as low voltage LOCMOS and TTL to high voltage LOCMOS. It has four data inputs (I0 to I3), an active HIGH output enable input (EO), four data outputs (O0 to O3) and their complements (O0 to O3). With EO HIGH, O0 to O3 and O0 to O3 are in the low impedance ON-state, either HIGH or LOW as determined by I0 to I3; with EO LOW, O0 to O3 and O0 to O3 are in the high impedance OFF-state. HEF4104B MSI The device uses a common negative supply (VSS) and separate positive supplies for inputs (VDDI) and outputs (VDD0). VDDI must always be less than or equal to VDDO, even during power turn-on and turn-off. For the permissible operating range of VDDI and VDDO see graph Fig.4. Each input protection circuit is terminated between VDDO and VSS. This allows the input signals to be driven from any potential between VDDO and VSS, without regard to curr.


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