HM-6518

HM-6518/883 March 1997 1024 x 1 CMOS RAM Description The HM-6518/883 is a 1024 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The HM-6518/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature. Features This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min TTL Compatible Input/Output High Output Drive - 2 TTL Loads High Noise Immunity On-Chip Address Register Two-Chip Selects for Easy Array Expansion Three-State Output Ordering Information PACKAGE CERDIP TEMP. RANGE -55oC to +125oC PART NUMBER HM1-6518/883 PKG. NO. F18.3 Pinout HM-6518/883 (CERDIP) TOP VIEW S1 E A0 A1 A2 A3 A4 Q GND 1 2 3 4 5 6 7 8 9 18 VCC 17 S2 16 D 15 W 14 A9 13 A8 12 A7 11 A6 10 A5 PIN A E W...