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HM3-6514S-9 Datasheet

1024 x 4 CMOS RAM

HM-6514 March 1997 1024 x 4 CMOS RAM Description The HM-6514 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses allowing efficient interfacing with microprocessor systems. The da.

Intersil Corporation
HM3-6514S-9.pdf

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Intersil Corporation HM3-6514S-9 Datasheet
HM-6514 March 1997 1024 x 4 CMOS RAM Description The HM-6514 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors. The HM-6514 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature. Features • Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max • Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max • Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min • TTL Compatible Input/Output • Common Data Input/Output • T.





HM-6514 March 1997 1024 x 4 CMOS RAM Description The HM-6514 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses allowing efficient interfacing with microprocessor systems. The da.

Intersil Corporation
HM3-6514S-9.pdf

Preview
Preview


Preview

Intersil Corporation HM3-6514S-9 Datasheet
HM-6514 March 1997 1024 x 4 CMOS RAM Description The HM-6514 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors. The HM-6514 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature. Features • Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max • Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max • Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min • TTL Compatible Input/Output • Common Data Input/Output • T.







 

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