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HM5212325FBPC-B60 Datasheet

128M LVTTL interface SDRAM 100 MHz 1-Mword x 32-bit x 4-bank PC/100 SDRAM

HM5212325FBPC-B60 128M LVTTL interface SDRAM 100 MHz 1-Mword × 32-bit × 4-bank PC/100 SDRAM ADE-203-1122C (Z) Rev. 1.0 May. 12 , 2000 Description The Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word × 32-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 90-bump fi.


Hitachi Semiconductor
HM5212325FBPC-B60.pdf

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Hitachi Semiconductor HM5212325FBPC-B60 Datasheet

HM5212325FBPC-B60 128M LVTTL interface SDRAM 100 MHz 1-Mword × 32-bit × 4-bank PC/100 SDRAM ADE-203-1122C (Z) Rev. 1.0 May. 12 , 2000 Description The Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word × 32-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 90-bump fine pitch BGA. Features • • • • • • • • • Single chip wide bit solution (× 32) 3.3 V power supply Clock frequency: 100 MHz (max) LVTTL interface Extremely small foot print: 0.8 mm pitch  Package: FBGA (BP-90) 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 4/8/full page 2 variations of burst sequence  Sequential (BL = 4/8/full page)  Interleave (BL = 4/8) Programmable CAS latency: 2/3 Byte control by DQMB Refresh cycles: 4096 refresh cycles/64 ms • • • HM5212325FBPC-B60 • 2 variations of refresh  Auto refresh  Self refresh • Full.






HM5212325FBPC-B60 128M LVTTL interface SDRAM 100 MHz 1-Mword × 32-bit × 4-bank PC/100 SDRAM ADE-203-1122C (Z) Rev. 1.0 May. 12 , 2000 Description The Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word × 32-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 90-bump fi.


Hitachi Semiconductor
HM5212325FBPC-B60.pdf

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Hitachi Semiconductor HM5212325FBPC-B60 Datasheet

HM5212325FBPC-B60 128M LVTTL interface SDRAM 100 MHz 1-Mword × 32-bit × 4-bank PC/100 SDRAM ADE-203-1122C (Z) Rev. 1.0 May. 12 , 2000 Description The Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word × 32-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 90-bump fine pitch BGA. Features • • • • • • • • • Single chip wide bit solution (× 32) 3.3 V power supply Clock frequency: 100 MHz (max) LVTTL interface Extremely small foot print: 0.8 mm pitch  Package: FBGA (BP-90) 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 4/8/full page 2 variations of burst sequence  Sequential (BL = 4/8/full page)  Interleave (BL = 4/8) Programmable CAS latency: 2/3 Byte control by DQMB Refresh cycles: 4096 refresh cycles/64 ms • • • HM5212325FBPC-B60 • 2 variations of refresh  Auto refresh  Self refresh • Full.








 

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