HM62V8512C

HM62V8512C Series 4 M SRAM (512-kword × 8-bit) ADE-203-1210A (Z) Rev. 1.0 Jan. 31, 2001 Description The Hitachi HM62V8512C is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II is available for high density mounting. The HM62V8512C is suitable for battery backup system. Features Single 3.0 V supply: 2.7 V to 3.6 V Access time: 55/70 ns (max) Power dissipation  Active: 6.0 mW/MHz (typ)  Standby: 2.4 µW (typ) Completely static memory. No clock or timing strobe required Equal access and cycle times Common data input and output: Three state output Directly LV-TTL compatible: All inputs Battery backup operation HM62V8512C Series Ordering Information Type No. HM62V8512CLFP-5 HM62V8512CLFP-7 HM62V8512CLFP-5SL HM62V8512CLFP-7SL HM62V8512CLTT-5 HM62V8512CLTT-7 HM62V8512CLTT-5SL HM62V8512CLTT-7SL HM62V8512CLRR-5 HM62V8512CLRR-7 HM62V8512CLRR-5SL HM62V8512CLRR-7SL Access time 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 400-mil 32-pin plastic TSOP II reverse (TTP-32DR) 400-mil 32-pin plastic TSOP II (TTP-32D) Package 525-mil 32-pin plastic SOP (FP-32D) 2 HM62V8512C Series Pin Arrangement 32-pin SOP A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 2...