HS9-81C56RH

HS-81C55RH, HS-81C56RH March 1996 Radiation Hardened 256 x 8 CMOS RAM Description The HS-81C55/56RH are radiation hardened RAM and I/O chips fabricated using the Intersil radiation hardened SelfAligned Junction Isolated (SAJI) silicon gate technology. Latch-up free operation is achieved by the use of epitaxial starting material to eliminate the parasitic SCR effect seen in conventional bulk CMOS devices. The HS-81C55/56RH is intended for use with the HS-80C85RH radiation hardened microprocessor system. The RAM portion is designed as 2048 static cells organized as 256 x 8. A maximum post irradiation access time of 500ns allows the HS-81C55/56RH to be used with the HS-80C85RH CPU without any wait states. The HS-81C55RH requires an active low chip enable while the HS-81C56RH requires an active high chip enable. These chips are designed for operation utilizing a single 5V power supply. Features Devices QML Qualified in Accordance with MIL-PRF-38535 Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95818 and Intersil’ QM Plan Radiation Hardened EPI-CMOS - Parametrics Guaranteed 1 x 105 RAD(Si) - Transient Upset > 1 x 108 RAD(Si)/s - Latch-Up Free > 1 x 1012 RAD(Si)/s Electrically Equivalent to Sandia SA 3001 Pin Compatible with Intel 8155/56 Bus Compatible with HS-80C85RH Single 5V Power Supply Low Standby Current 200µA Max Low Operating Current 2mA/MHz Completely Static Design Internal Address Latches Two Programmable 8-Bit I/O Por...