Oscillator. HSP45102 Datasheet

HSP45102 Datasheet PDF

Part HSP45102
Description 12-Bit Numerically Controlled Oscillator
Feature HSP45102 Data Sheet January 1999 File Number 2810.6 12-Bit Numerically Controlled Oscillator The In.
Manufacture Intersil Corporation
Datasheet
Download HSP45102 Datasheet

HSP45102 Data Sheet January 1999 File Number 2810.6 12-Bit HSP45102 Datasheet




HSP45102
Data Sheet
HSP45102
January 1999 File Number 2810.6
12-Bit Numerically Controlled Oscillator
The Intersil HSP45102 is Numerically Controlled Oscillator
(NCO12) with 32-bit frequency resolution and 12-bit output.
With over 69dB of spurious free dynamic range and worst
case frequency resolution of 0.009Hz, the NCO12 provides
significant accuracy for frequency synthesis solutions at a
competitive price.
The frequency to be generated is selected from two frequency
control words. A single control pin selects which word is used
to determine the output frequency. Switching from one
frequency to another occurs in one clock cycle, with a 6 clock
pipeline delay from the time that the new control word is
loaded until t3-he new frequency appears on the output.
Two pins, P0-1, are provided for phase modulation. They are
encoded and added to the top two bits of the phase
accumulator to offset the phase in 90o increments.
The 13-bit output of the Phase Offset Adder is mapped to
the sine wave amplitude via the Sine ROM. The output data
format is offset binary to simplify interfacing to D/A
converters. Spurious frequency components in the output
sinusoid are less than -69dBc.
The NCO12 has applications as a Direct Digital Synthesizer
and modulator in low cost digital radios, satellite terminals,
and function generators.
Features
• 33MHz, 40MHz Versions
• 32-Bit Frequency Control
• BFSK, QPSK Modulation
• Serial Frequency Load
• 12-Bit Sine Output
• Offset Binary Output Format
• 0.009Hz Tuning Resolution at 40MHz
• Spurious Frequency Components <-69dBc
• Fully Static CMOS
• Low Cost
Applications
• Direct Digital Synthesis
• Modulation
• PSK Communications
• Related Products
- HI5731 12-Bit, 100MHz D/A Converter
Ordering Information
PART NUMBER
HSP45102PC-33
HSP45102PC-40
HSP45102SC-33
HSP45102SC-40
HSP45102SI-33
TEMP.
RANGE (oC)
PACKAGE
0 to 70 28 Ld PDIP
0 to 70 28 Ld PDIP
0 to 70 28 Ld SOIC
0 to 70 28 Ld SOIC
-40 to 85 28 Ld SOIC
PKG.
NO.
E28.6
E28.6
M28.3
M28.3
M28.3
Block Diagram
CLK
PO-1
MSB/ LSB
SFTEN
SD
SCLK
FREQUENCY
CONTROL
SECTION
32
PHASE
32 ACCUMULATOR 13
PHASE
OFFSET
ADDER
13 SINE 12
ROM
OUT0-11
LOAD
TXFR
ENPHAC
SEL_L / M
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999



HSP45102
Pinout
HSP45102
28 LEAD PDIP, 28 LEAD SOIC
TOP VIEW
OUT6 1
OUT7 2
OUT8 3
OUT9 4
OUT10 5
OUT11 6
GND 7
VCC 8
SEL_L/M 9
SFTEN 10
MSB/LSB 11
ENPHAC 12
SD 13
SCLK 14
28 OUT5
27 OUT4
26 OUT3
25 OUT2
24 OUT1
23 OUT0
22 VCC
21 GND
20 P0
19 P1
18 LOAD
17 TXFR
16 CLK
15 GND
Pin Description
NAME
TYPE
DESCRIPTION
VCC
GND
+5V power supply pin.
Ground
P0-1
I Phase modulation inputs (become active after a pipeline delay of four clocks). A phase shift of 0, 90,
180, or 270 degrees can be selected as shown in Table 1.
CLK I NCO clock. (CMOS level)
SCLK
I This pin clocks the frequency control shift register.
SEL_L/ M
I A high on this input selects the least significant 32 bits of the 64-bit frequency register as the input to
the phase accumulator; a low selects the most significant 32 bits.
SFTEN
I The active low input enables the shifting of the frequency register.
MSB/ LSB
I This input selects the shift direction of the frequency register. A low on this input shifts in the data LSB
first; a high shifts in the data MSB first.
ENPHAC
I This pin, when low, enables the clocking of the Phase Accumulator. This input has a pipeline delay of
four clocks.
SD I Data on this pin is shifted into the frequency register by the rising edge of SCLK when SFTEN is low.
TXFR
I This active low input is clocked onto the chip by CLK and becomes active after a pipeline delay of four
clocks. When low, the frequency control word selected by SEL_L/M is transferred from the frequency
register to the phase accumulator’s input register.
LOAD
I This input becomes active after a pipeline delay of five clocks. When low, the feedback in the phase
accumulator is zeroed.
OUT0-11
O Output data. OUT0 is LSB. Unsigned.
All inputs are TTL level, with the exception of CLK.
Overline designates active low signals.
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