HYMP112S64MP8

www.DataSheet4U.com DDR2 SDRAM SO-DIMM HYMP112S64(L)MP8 Revision History No. 0.1 History 1) Defined target spec. 2) Corrected Pin assignment table Date July 2004 Remark 128Mx64 bits This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/ July 2004 1 www.DataSheet4U.com DDR2 SDRAM SO-DIMM HYMP112S64(L)MP8 DESCRIPTION 128Mx64 bits Hynix HYMP112S64MP8 series is unbuffered 200-pin double data rate 2 Synchronous DRAM Small Outline Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx64 high-speed memory arrays. Hynix HYMP112S64MP8 series consists of eight 128Mx8 DDR2 SDRAMs in 63 ball FBGA Dual Die Pacakge(DDP)s. Hynix HYMP112S64MP8 series provide a high performance 8-byte interface in 67.60mm X 30.00mm form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMP512S64MP8 series is designed for high speed and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 4bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_1.8. High speed frequenci...