IBM0436A41BLAB

. www.DataSheet4U.com Preliminary Features IBM0418A81BLAB IBM0436A81BLAB IBM0418A41BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations 0.25 Micron CMOS technology Synchronous Pipeline Mode of Operation with Self-Timed Late Write Single Differential HSTL Clock +2.5V Power Supply, Ground, 1.5, 1.8V VDDQ, and 0.90V VREF HSTL Input and Output levels Registered Addresses, Write Enables, Synchronous Select, and Data Ins Registered Outputs Common I/O Asynchronous Output Enable Synchronous Power Down Input Boundary Scan using limited set of JTAG 1149.1 functions Byte Write Capability and Global Write Enable 7 x 17 Bump Ball Grid Array Package with SRAM JEDEC Standard Pinout and Boundary SCAN Order Description The 4Mb and 8Mb SRAMs—IBM0436A41BLAB, IBM0418A41BLAB, IBM0418A81BLAB, and IBM0436A81BLAB—are Synchronous Pipeline Mode, high-performance CMOS Static Random Access Memories that are versatile, wide I/O, and can achieve 3ns cycle times. Differential K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of the K clock, all Addresses, Write-Enables, Sync Select, and Data Ins are registered internally. Data Outs are updated from output registers off the next rising edge of the K clock. An internal Write buffer allows write data to follow one cycle after addresses and controls. The ...