IC41C16105

IC41C16105 IC41LV16105 .EATURES 1M x 16 (16-MBIT) DYNAMIC RAM WITH .AST PAGE MODE • TTL compatible inputs and outputs; tristate I/O • Refresh Interval: 1,024 cycles/16 ms • Refresh Mode: RAS-Only, CAS-before-RAS (CBR), Hidden • JEDEC standard pinout • Single power supply: 5V ± 10% (IC41C16105) 3.3V ± 10% (IC41LV16105) • Byte Write and Byte Read operation via two CAS • Industrail temperature range -40oC to 85oC DESCRIPTION The 1+51 IC41C16105 and IC41LV16105 are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. .ast Page Mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the IC41C16105 ideal for use in 16-, 32-bit wide data bus systems. These features make the IC41C16105 and IC41LV16105 ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IC41C16105 and IC41LV16105 are packaged in a 42-pin 400mil SOJ and 400mil 44- (50-) pin TSOP-2. KEY TIMING PARAMETERS Parameter Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. .ast Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) -50 50 13 25 20 84 -60 60 15 30 25 104 Unit ns ns ns ns ns PIN CON.IGURATIONS 44(50)-Pin TSOP-2 VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC NC WE RAS NC NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22...