IC42S32200

IC42S32200 IC42S32200L Document Title 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM Revision History www.datasheet4u.com Revision No History Initial Draft Obselete partial refresh function Obselete 5ns speed grade Change ICC3P from 3mA to 5mA Revise typo Revise p.20,p.22 data and p.28 typo Draft Date September 26,2002 September 05,2003 April 27,2004 February 04,2005 Remark 0A 0B 0C 0D The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. DR036-0D 02/04/2005 1 IC42S32200 IC42S32200L 512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES · Concurrent auto www.datasheet4u.com precharge · Clock rate:166/143/125 MHz · Fully synchronous operation · Internal pipelined architecture · Four internal banks (512K x 32bit x 4bank) · Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:interleaved or linear burst -Burst-Read-Single-Write · Burst stop function · Individual byte controlled by DQM0-3 · Auto Refresh and Self Refresh · 4096 refresh cycles/64ms · Single +3.3V ±0.3V power supply · Interface:LVTTL · Package:400 x 875 mil,86 Pin TSOP-2,0.50mm Pin Pitch and 11x13mm, 90 Ball BGA, Ball pitch 0.8mm · Pb-free package is available. DESCRIPTION The ICSI IC42S32200 and IC42S32200L is a high-speed CMOS configure...